Date: Wednesday, December 12, 2018
Intel often comes across as a gargantuan soulless company, and on many fronts it has earned that reputation. However, yesterday afternoon, the man that has been driving the ship over at Intel, Murthy Renduchintala (Group President Technology, Systems Architecture & Client Group Chief Engineering Officer) clearly expressed a sentence that made me realize that we are not the only ones that know Intel has a lot of ground to make up. Murthy said in relation to it 10nm process failures, "We have some humble pie to eat, and we are eating it." This alone should tell you that we are not dealing with the Intel of old.
Intel is taking its core models for how it operates internally, scattering those to the wind in Thanos fashion, and updating how it does business. After roadmaps that have focused on 10nm process have become a joke in the industry, Intel is adopting a workflow that will make the roadmap its one rule, which will certainly please its customers. "One of the things you will see more amplified, is schedule predictability." Along with this Murthy proclaims that Intel now has in place, "Aggressive risks with clear contingencies." This marks a huge shift in how Intel does business. The days of process node, architecture, and other IP being tied together as a end point are over. He explains that Intel's failure to meet it previous 10nm roadmaps, has been a teaching tool in how it needs to move forward.
What this all means is that process nodes will have overlaps and quite simply some nodes are not well matched with certain IP. As mentioned above, Intel plans to push forward aggressively (How often have you heard Intel use the word "aggressively?"), but will no longer leave itself without an out if all those aggressive plans do not actually work out into sellable product that its customers want. The entire "package" of Intel technology attached to a firm production date has become priority over simply producing a specific node using a specific architecture and happening whenever that is possible. This will assuredly make Intel much more agile in the future and give it a flexibility and market position that it has never had before.
While Jim did not have as much to say to the group as a whole during our day, he did tell us something in a breakout session that made an impact on me. I am paraphrasing here, but this is still very much on point. Keller would ask for something to be done, and the reply would be that the person he was asking would try to have it back to him in a month. Keller then said, "I was thinking more like tomorrow." This outlines that Keller is introducing a sense of urgency that is not par for the course at Intel. Intel has been a monolithic bureaucratic beast that has been slow to react, and I get the sense that is changing. That is not to say that any of its rivals are huge sharks that are about to take big chunks out of its earnings calls, but it looks like now Intel is finally tiring of batting away the wayward piranha, and will not be waiting for the entire school to arrive. Keller also very much touched on wanting Intel's engineers to "have fun" as well, seemingly wanting to foster an environment of creativity again. He did remark that he did not think it was too much fun to go to work every day just looking to squeeze out that 5% IPC gain per new product that we have seen out of Intel for so long now.
Raja Koduri took his time and introduced us to Intel's new 6 Pillar philosophy. This represents a strategic shift from the days of old when it comes to Intel's design and engineering models.
1. Process - Access to leadership process technology remains essential to building leadership products. Advanced packaging solutions will enable Intel to continue exponential scaling in computing density by extending transistor density to the third dimension.
2. Architecture - The future is a diverse mix of scalar, vector, matrix and spatial architectures deployed in CPU, GPU, accelerator and FPGA sockets, enabled by a scalable software stack, integrated into systems by advanced packaging technology.
3. Memory - High-capacity, high-speed storage is crucial for next-generation computing workloads. Intel is uniquely positioned to combine in-package memory and Intel Optane technology to fill gaps in the memory hierarchy to provide bandwidth closer to the silicon die.
4. Interconnect - Communication scales from wireless connections for 5G infrastructure to silicon-level package and die interconnects. Only by offering a complete range of leading interconnect products enables the heterogeneous computing landscape at scale.
5. Security - With the emergence of new threats, Intel has all the components to build a "better together" security strategy. Intel is uniquely positioned to deliver security technologies that help improve the end-to-end and to make security advancements a key differentiator.
6. Software - For every order of magnitude performance potential of a new hardware architecture there are two orders of magnitude performance enabled by software. A common set of tools that can address Intel silicon for developers is critical to exponential scaling.
Over the day, Intel covered somewhere between 120 and 150 slides showcasing different parts of its new 6 Pillar Strategy, which is much too much to dive into here with only a short night to cover this. I am going to break down what I think is going to be most important, and exciting to HardOCP readers.
What Intel is calling "Foveros" is surely the most exciting news we got all day. Intel explained that we would see products with this stacking technique towards the end of 2019. This is very much a "chiplet" approach, but instead of moving out around a central controller, Intel is looking to keep this nice and neat inside a very small 12mm X 12mm package for the time being. With the initial Foveros chips, we have the integration of both 22nm and 10nm logic in the stack. This puts most of our IO and other controllers at 22nm, with 10nm CPU, GPU, and other logic that benefits from the 10nm process in both power reduction and a bump in clock.
"Foveros" is a new 3D technology invented at Intel that allows logic chips to be stacked for the first time, helping deliver high compute density and enabling a complete rethinking of system architecture.
While the graphics above did not outline this, the slides shown to use did in fact show a final layer of DRAM being added to the stack as well.
Intel did even show us currently working Foveros silicon working in a live demonstration. Raja explained that this current Foveros product was specifically designed for a customer and was likely to soon go into production, if it was not already in production. Given that Raja had no qualms about the timeline of Foveros product next year, it made me guess that Intel was very much on track with this Foveros process overall.
While Raja was not specific about exactly what product we would see first use the Foveros process, it did feel very much like we would see Intel's next-gen Sunny Cove architecture showcasing it. Time will surely tell.
The technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller "chiplets," where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.
Intel expects to launch a range of products using Foveros beginning in the second half of 2019. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. It will enable the combination of world-class performance and power efficiency in a small form factor.
Intel is adding Foveros to its toolbox, and of course relying on older process technology as well. I did ask Raja if we would see 10nm monolithic processors in Intel's future and he assured me that we would. Specifically he mentioned monolithic die mobile processors at the high end in Intel designs. While I do not remember this being discussed during the day, Intel did send over a PDF that outlined 2D integration of chipsets as well that I found in my inbox after the meeting was over. This very much looks like AMD's recent chipset solutions we have seen. Doing 2D chiplets would assuredly allow Intel even more flexibility in its design process..."Aggressive risks with clear contingencies."
2D INTEGRATION - Combine IPs built with separate processes into a single package with Intel EMIB, helping improve yield, cost, time-to-market, and total capability.
Intel's new Sunny Cove architecture was promised to be "deeper, wider, and smarter" than the current Skylake architecture. It was interesting to see Intel use its own previous architecture as the measuring stick.
New Sunny Cove CPU Architecture: Intel introduced Sunny Cove, Intel’s next-generation CPU microarchitecture designed to increase performance per clock and power efficiency for general purpose computing tasks, and includes new features to accelerate special purpose computing tasks like AI and cryptography. Sunny Cove will be the basis for Intel’s next-generation server (Intel Xeon) and client (Intel Core) processors later next year. Sunny Cove features include:
Enhanced microarchitecture to execute more operations in parallel.
New algorithms to reduce latency.
Increased size of key buffers and caches to optimize data-centric workloads.
Architectural extensions for specific use cases and algorithms. For example, new performance-boosting instructions for cryptography, such as vector AES and SHA-NI, and other critical use cases like compression and decompression.
Sunny Cove enables reduced latency and high throughput, as well as offers much greater parallelism that is expected to improve experiences from gaming to media to data-centric applications.
We did also get to see a demo of Sunny Cove in action running a 7 Zip demonstration against a Skylake CPU. Intel noted that the Sunny Cove CPU was 75% faster in this particular application.
A lot of emphasis was put forth that a lot of thought had gone into Sunny Cove and its usage in SHA and cryptographic applications.
Willow Cove and Golden Cove architectures were also mentioned on the below roadmap slide, however no details beyond what are on the slide were given.
While a lot of time was spent on the upcoming iGPU from Intel, it will do little to excite the HardOCP crowd, that said, it will be Intel's first Teraflop part, and actually looks to be up to playing some games as Intel is saying it is 2X the performance of its previous iGPU. Worth mentioning Gen 11 is ~75% of the size of Gen 9 and uses 25% less power than Gen 9 as well.
Next-Generation Graphics: Intel unveiled new Gen11 integrated graphics with 64 enhanced execution units, more than double previous Intel Gen9 graphics (24 EUs), designed to break the 1 TFLOPS barrier. The new integrated graphics will be delivered in 10nm-based processors beginning in 2019.
Interestingly enough, Intel did show us "Coarse Pixel Shading" working on the Gen 11 parts as well, which is very much akin to the examples of foveated rendering that we see used in AR/VR by NVIDIA. Intel was quick to point out that it had developed the technology under Open Source licensing over 4 years ago. The demo below shows CPS working in an Unreal Engine based demo.
While we were told not to expect any information on Intel next-gen graphics, Intel did very much let us know that what looks to be its official brand name in place. The slides speak for themselves, but we all truly did expect a fully new GPU architecture out of Intel. I would suspect that we should expect there to be little fanfare around its first discrete GPU to market in 2020. It will likely be a mid to low end part for the masses. After that I would expect we will start seeing Intel swinging for the fences in 2022.
I will not spent a lot of time on this, but this will be a defining moment in time when Intel pulls this off. Raja wants to pull every product the company has under one API. If you can program for one, you can program for all...scalar/CPU, vector/GPU, matrix/AI, and spatial/FPGA. Intel currently have about 15,800 software engineers working for it, many headed in different directions. Raja said, "We now have a huge religion around software at Intel in the last 12 months," and he added we are "doubling down on software investments."
"One API" Software: Intel announced the "One API" project to simplify the programming of diverse computing engines across CPU, GPU, FPGA, AI and other accelerators. The project includes a comprehensive and unified portfolio of developer tools for mapping software to the hardware that can best accelerate the code. A public project release is expected to be available in 2019.
Murthy sent us on our way with the roundup slides below. As mentioned, there were around 150 slides presented to us throughout the day, so I will assure you that other sites will have other coverage of information that we did not get to here.
When I asked about Spectre in our round table meeting, I was quickly hushed. For one thing I was out of turn, but I do know that I was never called on for a follow up to Spectre either. Raja did tell me that it would be covered after lunch however. This is the full breadth of information that we were given on hardware solutions for Spectre. Its seems that the first products with hardware mitigation for Spectre v3 are already shipping, however, we were not told what those products were exactly. We were told that Cascade Lake would have fixes for Spectre v2. And that was all that was said.
While there is a lot of information to still digest and unpack from our day with Intel, I think the biggest takeaway is how Intel is decoupling its node process from its architecture. That is a huge move away from Intel's previous business plans and I have to say I like it. Assuredly, 10nm process failures have taught Intel some lessons over the last couple of years. The 3D chip stacking is of course very exciting as well. What we got today was very much a 10,000 foot view or as Raja put it, "an Xray into what is coming." We do expect to see Intel with some specific product launches at CES in early January, but for now, we are not sure of what those are.
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